Detecting Micro Cracks on Sidewall of WLCSP
Eliminate defects for improved quality, performance, and longevity of the chip
Wafer Level Chip Scale Packages (WLCSPs) have multiple layers and can develop micro cracks from damage caused by poor handling, excessive stress (i.e., mounting of solder balls), or rough transport. If undetected early in the process, these cracks can affect the quality, performance, and longevity of the chip.
Because of these structural risks, WLCSPs should be inspected. When checking for defects along the sidewall of the WLCSP, it is hard to know the difference between a layer change and a micro crack. Making this distinction is difficult for rule-based machine vision because there are confusing patterns when viewing the WLCSP from the side due to noisy and low contrast backgrounds. For instance, cracks are in different locations and can look like irregular lines of structural layers.
Trying to correctly detect micro cracks in WLCSPs using rule-based machine vision is time-consuming and challenging. Cognex Deep Learning tools more efficiently detect micro cracks by applying intelligent algorithms to learn the differences between normal structural layers and defects.
The software is trained with a range of images showing micro cracks as well as image sets showing the normal layering within WLCSPs. The defect detection tool learns the normal layer variation and develops a comprehensive understanding of the defects (micro cracks).
Using deep learning, highly accurate inspections increase the yield of good chip packages that might have been mistakenly classified as No Good (NG). Conversely, deep learning can detect micro cracks on WLCSPs that would have otherwise passed inspection from traditional methods, only to prematurely fail in the field.